In EEPROM memories it is necessary that the high voltage levels in the order of 12 or 15 V generated by the charge pump for programming and deletion operations are maintained at a virtually constant value whatever current delivery is required (the so-called driving capability), which is normally in the order of dozens of microamperes. This enables a stable and known output voltage to be available that does not exceed the limits set by the dielectric strength of the oxides, of the transistors and of the capacitors, with the risk of damaging them permanently by producing perforations.
A typical initial wiring diagram is shown in FIG. 1, in which a charge pump 1 generates an output voltage Vout sent to a comparator 2, which compares the voltage Vout with a voltage Vreg. Vreg is the desired regulating voltage generated from a known and extremely stable reference voltage, for example a BandGap circuit. If Vout>Vreg, the comparator 2 sends a logic signal Von to a control circuit 3, having a clock input pulse CLOCK, that blocks transmission of the CLOCK pulses to a phase generator 4 suitable for supplying the charge pump 1. Thus the charge pump 1 starts to discharge until the voltage Vout becomes less than the voltage Vreg. By means of said feedback a dynamic equilibrium is reached that determines the steady state Vout=Vreg. Once the regulating condition has been reached, the charge pump 1, if it is a vacuum pump, is switched off in order to not dissipate power unnecessarily. In the presence of a charge that requires current, the circuit lets the clock pulses pass so as to compensate for the decrease in output voltage Vout due to the delivered charge.
In order to obtain the signal Von, a circuit is used as shown in FIG. 2. The circuit comprises a resistive divider formed by the series of two resistances Rup and Rdown arranged between Vout and ground GND. The voltage Vr at the heads of the resistance Rdown is sampled and compared with a reference voltage Vbg supplied by a bandgap circuit by means of a comparator 5. The signal at the comparator output is the signal Von that allows or does not allow the passage of the clock pulses CLOCK from the circuit 3 to the phase generator 4. As shown in FIG. 2, two capacitors Cup and Cdown are arranged at the heads of the respective resistances Rup and Rdown and necessary for compensating parasitic capacity.
The regulating voltage obtained as an average value arises from Vout=Vbg*(1+Rup/Rdown). The circuit disclosed in FIGS. 1 and 2 is used both for the charge pump used in the reading operations of the EEPROM memories and for the charge pump used in the writing operations thereof.
The output voltage of the charge pump is carried on the memory cells in ramp mode so as not to risk breakage of the oxide layers of the memory cells. Normally the ramp generator charges a capacitor with a direct current to obtain a linear increase. In FIG. 3 there is shown a typical diagram of the regulation of the charge pump with a ramp generating circuit used for the EEPROM cells. The ramp generating circuit comprises an operational amplifier 6 having the input voltage Vbg on the inverting terminal and the voltage Vbot on the non-inverting terminal. The output of the operational amplifier 6 controls a transistor PMOS M1 having the source terminal connected to the output voltage Vout from the charge pump 3 of the circuit in FIG. 1. The drain terminal LS of the transistor M1 is connected to a capacitor C1 having the other terminal connected to the voltage Vbot at the heads of a current generator Ic connected to ground GND. The node LS is charged at a constant tilt equal to Ic/C1. By modulating the current, the ascent speed of the voltage is varied appropriately.
The node LS controls a first plurality of transistors identical to the plurality of transistors suitable for selecting the memory cells. Each selection transistor has the voltage LS on the gate terminal while the voltage on the source terminal of each transistor of the first plurality is the same as the ramp voltage Vramp decreased of the threshold voltage of the transistor. In this way, coupling of the voltage Vramp and the voltage actually present on the memory cells is assured. In the diagram of FIG. 3 it is shown that the regulating node controlled directly is the node VP0 and the output voltage Vout of the charge pump is controlled indirectly through the transistors 125 that, through the coupling with those of the latch part of the memory cells and with the selection transistors of the memory cells, replicate exactly the programming and deletion path. As said transistors that are a copy of the latch part and of the selection transistors are in the ramp generator, by regulating the node VP0 also the voltage Vramp is regulated, as VP0 is the maximum value of Vramp except for decoupling between the paths of the voltages in play.
Nevertheless, for example, during the memory cell programming phase, a voltage drop may be generated on the selection transistors that distances the voltage level Vramp from the expected value. Furthermore, the copy of the latch and selection transistors waste space.
Thus there remains a need for an integrated control circuit for a charge pump that overcomes the aforementioned drawbacks.